CALL FOR PARTICIPATION CASES 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems http://www.crest.gatech.edu/conferences/cases2002 October 8-11, 2002 Grenoble, France co-located with EMSOFT 2002 (Oct 7-9) http://www-emsoft02.imag.fr/ REGISTRATION DATES Early registration: $375 (before Sept 17, 2002) Early student: $225 (before Sept 17, 2002) Late registration: $450 Late student: $275 If already registered for EMSOFT: $200 Please register through the web site. CONFERENCE PROGRAM ------------------------------------------------------------------------------- Tuesday, October 8, 2002 ------------------------------------------------------------------------------- 8:30 - 12:00 Tutorial 1: Compilers for Embedded Processors: Technology and New Challenges Presenter: Rainer Leupers, Aachen University of Technology abstracts below 13:30 - 17:00 Tutorial 2: Software Performance Analysis for Real-Time Embedded Systems Presenters: Rolf Ernst, Technical University of Braunschweig Reinhard Wilhelm, University of Saarbr¡?cken abstracts below ------------------------------------------------------------------------------- Wednesday, October 9, 2002 ------------------------------------------------------------------------------- 14:00 - 15:30 Keynote 1: Giovanni De Micheli (Stanford University), Joint Talk CASES'02/EMSOFT'02 Keynote 2: John Rayfield (ARM Ltd.), Joint Talk CASES'02/EMSOFT'02 16:00 - 17:30 Invited Talks Physical Programming: Beyond Mere Logic Bran Selic, Rationale Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis Luciano Lavagno, Politecnico di Torino and Cadence Labs Compiling with Code-Size Constraints Jens Palsberg, Purdue University ------------------------------------------------------------------------------- Thursday, October 10, 2002 ------------------------------------------------------------------------------- 8:30 - 10:30 Session 2 Embedded System Techniques (1) A Case for Dynamic Pipeline Scaling Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg Dept of Electrical and Computer Engineering, North Carolina State University, USA A Near-Optimal Instruction Scheduler for A Tightly Constrained, Variable Instruction Set Embedded Processor Jack Liu, Fred Chow Cognigine Corporation, USA Components for Embedded Software - The PECOS approach Thomas Genssler, Forschungszentrum Informatik (FZI), Germany Oscar Nierstrasz, Software Composition Group S(CG), University of Bern, Switzerland Bastiaan Schoenhage, Object Technology International (OTI), The Netherlands Efficient Architecture/Compiler Co-Exploration for ASIPs Dirk Fischer, Juergen Teich, Michael Thies, Ralph Weper University of Paderborn, Germany 11:00 - 12:30 Session 3 (Parallel Tracks) 11:00 - 12:30 Session 3 Track 1 Architecture Adaptation and Synthesis Cycle-time Aware Architecture Synthesis of Custom Hardware Accelerators Mukud Sivaraman, Shail Aditya Hewlett-Packard Labs, USA An Adaptive CMP Architecture for Future Mobile Terminals Mladen Nikitovic, Mats Brorsson Department of Microelectronics and Information Technology, Royal Institute of Technology (KTH), Sweden Towards Automatic Synthesis of a Class of Application-Specific Sensor Networks Amol Bakshi, Jingzhao Ou, Viktor K. Prasanna Dept. of EE-Systems, University of Southern California, USA 11:00 - 12:30 Session 3 Track 2 Extensions and Benchmarks Hardware Implementation of the Ravenscar Ada Tasking Profile) Michael Ward and Neil C. Audsley Dept. Computer Science, University of York, U.K. Bit Section Instruction Set Extension of ARM for Embedded Applications Bengu Li and Rajiv Gupta Department of Computer Science, University of Arizona, USA Code coverage and input variability: effects on architecture and compiler Hillery C. Hunter and Wen-mei W. Hwu University of Illinois at Urbana-Champaign, USA 12:30 - 14:00 Lunch 14:00 - 15:30 Session 4 (Parallel Tracks) 14:00 - 15:30 Session 4 Track 1 Power in Memory and Network Processors An Integrated Approach to Reducing Power Dissipation in Memory Hierarchies Jay Pisharath, Alok Choudhary Department of Electrical and Computer Engineering, Northwestern University, USA Embedded Cache Architecture with Programmable Write Buffer Support for Power and Performance Flexibility Afzal Malik, Bill Moyer, Roger Zhou Embedded Platform Solutions, Motorola Inc., USA Increasing Power Efficiency of Multi-Core Network Processors through Data Filtering Gokhan Memik, William H. Mangione-Smith Department of Electrical Engineering, University of California, Los Angeles, USA 14:00 - 15:30 Session 4 Track 2 Program Transformations Cost Effective Memory Disambiguation for Multimedia Codes Esther Salam¡?, Jes¡ñs Corbal, Carlos ¡?lvarez and Mateo Valero Departament d'Arquitectura de Computadors, Universitat Polit¡?cnica de Catalunya, Spain Optimizing Inter-Nest Data Locality M. Kandemir, I. Kadayif, Microsystems Design Lab, Pennsylvania State University, USA A. Choudhary, J. A. Zambreno, ECE Department, Northwestern University, USA Leakage-Proof Program Partitioning Tao Zhang, Santosh Pande, Andre dos Satos, Georgia Institute of Technology, College of Computing, USA Franz Josef Bruecklmayr, Infineon Technologies, Germany 16:00 - 17:00 Session 5 Panel "Embedded Architectures: Configurable, Re-configurable, ... or what ?" 17:00 - 18:30 Session 6 (Parallel Tracks) 17:00 - 18:30 Session 6 Track 1 Scheduling and Frequency Scaling for Power Dynamic Voltage Leveling Scheduling for Real-Time Embedded Systems on Low-Power Variable Speed Processors Jian-Liang Kuo and Tien-Fu Chen Department of Computer Science, National Chung Cheng University, Taiwan Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads Zhijian Lu, Jason Hein, Mircea Stan, John Lach, Dept. of Electrical and Computer Engineering, University of Virginia, USA Kevin Skadron, Marty Humphrey, Department of Computer Science, University of Virginia, USA Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems Ravindra Jejurikar and Rajesh Gupta Center for Embedded Computer Systems, Department of Information and Computer Science, University of California at Irvine, USA 17:00 - 18:30 Session 6 Track 2 Compilers and Program Analysis Scenario-Based Software Characterization as a Contingency to Traditional Program Profiling Jeffry T Russell, Margarida F Jacome University of Texas at Austin, Dept ECE, USA Experience with a Retargetable Compiler for a Commercial Network Processor Jinhwan Kim, Sungjoon Jung, Yunheung Park, Electrical Engineering & Computer Science Department, Korea Advanced Institute of Science & Technology, Korea Gang-Ryung Uh, Agere Systems, USA PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations Alex Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok Choudhary, Prith Banerjee Center for Parallel and Distributed Computing, Technological Institute, Northwestern University, USA ------------------------------------------------------------------------------- Friday, October 11, 2002 ------------------------------------------------------------------------------- 8:30 - 10:30 Session 7 Embedded System Techniques (2) Wave Pipelining for Application-Specific Networks-on-Chips Jiang Xu, Wayne Wolf Dept. of Electrical Engineering, Princeton University, USA Handling of Packet Dependencies: A Critical Issue for Highly Parallel Network Processors Stephen Melvin, FlowStorm, Inc., USA Yale Patt, University of Texas, USA On Achieving Balanced Power Consumption in Software Pipelined Loops Hongbo Yang, Guang R. Gao, Clement Leung University of Delaware, USA Low Power Control Techniques for TFT LCD Displays Franco Gatti, Andrea Acquaviva, Luca Benini, Bruno Ricco DEIS - University of Bologna, Italy 11:00 - 12:30 Session 8 (Parallel Tracks) 11:00 - 12:30 Session 8 Track 1 Power and Battery Management Dynamic Battery State Aware Approaches for Improving Battery Utilization Sung I. Park, Mani B. Srivastava Networked and Embedded Systems Laboratory, Electrical Engineering Departments, University of California, Los Angeles, USA System Lifetime extension by battery management: an experimental work Davide Brui, Luca Benini, Bruno Ricc¡? D.E.I.S., University of Bologna, Italy Process Cruise Control - Event-Driven Clock Scaling for Dynamic Power Management Andreas Weissel, Frank Bellosa University of Erlangen, Germany 11:00 - 12:30 Session 8 Track 2 System Synthesis HW / SW partitioning approach for reconfigurable system design K. Ben Chehida ad M. Auguin I3S, University of Nice Sophia Antipolis, France An Efficient Technique for Exploring Register File Size in ASIP Synthesis Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar IIT, India Instruction Generation and Regularity Extraction for Reconfigurable Processors Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh Computer Science Department, University of California, Los Angeles, USA 12:30 - 14:00 Lunch 14:00 - 15:30 Session 9 (Parallel Tracks) 14:00 - 16:30 Session 9 Track 1 Software Transformation Automatic Floating-point to Fixed-point Conversion for DSP Code Generation Daniel Menard, Daniel Chillet, INRIA, LASTI University of Rennes 1, France Fran¡?ois Charot, Olivier Sentieys, INRIA, IRISA, France Iterative procedural abstraction for code size reduction Dae-Hwan Kim, Hyuk Jae Lee School of Electrical Engineering and Computer Science, Seoul National University, Korea Validating Software Pipelining Optimizations Raya Leviathan, Amir Pnueli Dept. of Computer Science, Weizmann Institute of Science, Israel 14:00 - 16:30 Session 9 Track 2 Embedded Programs Ensuring Code Safety Without Runtime Checks for Real-Time Control Systems Sumant Kowshik, Dinakar Dhurjati, Vikram Adve University of Illinois at Urbana-Champaign, USA Predictable Programs in Barcodes Alwyn Goodloe, Michael McDougall, Carl A. Gunter, Rajeev Alur Department of Computer and Information Science, University of Pennsylvania, USA Real Java for Real Time - Gain and Pain Anders Nilsson, Torbj¡?rn Ekman, Klas Nilsson Dept. of Computer Science, Lund University, Sweden TUTORIAL ABSTRACTS Tutorial 1: Compilers for Embedded Processors: Technology and New Challenges Tuesday, 8:30AM - 12Noon Presenter: Rainer Leupers, Aachen University of Technology Abstract: Programmable processors are among the major building blocks in today's embedded SoC designs. In contrast to desktop systems, there is a huge variety of domain specific and even application specific architectures, including microcontrollers, DSPs, NPUs, and ASIPs. The irregular architectures and very high code quality demands of embedded processors create a need for new compiler techniques beyond classical Dragon Book compilation. This tutorial gives an overview of today's retargetable compiler and code optimization technology for embedded processors, while also touching further important software development tools. Additionally, new research challenges in the areas of architecture exploration and compilation for recent architecture families like VLIWs and NPUs will be covered. Tutorial 2: Software Performance Analysis for Real-Time Embedded Systems Tuesday, 1:30PM - 5PM Presenters: Rolf Ernst, Technical University of Braunschweig Reinhard Wilhelm, University of Saarbr¡?cken Abstract: Run-time guarantees play an important role in the area of embedded systems and especially hard real-time systems. These systems are typically subject to stringent timing constraints which often result from the interaction with the surrounding physical environment. It is essential that the computations are completed within their associated time bounds; otherwise severe damages may result. Therefore, a schedulability analysis has to be performed which guarantees that all timing constraints will be met (also called timing validation). The complex processor architectural features, such as caches and pipelines make the analysis of the software execution behavior very difficult. In this tutorial, the approaches for computing reliable worst-case execution times for real-time software will be presented. Techniques for analyzing the overall system-level time behavior will also be discussed. ORGANIZING COMMITTEE Steering Committee: Guang R. Gao, University of Delaware Vinod Kathail, Hewlett-Packard Labs Edward Lee, University of California Berkeley Jaime Moreno, IBM T.J. Watson Research Center Krishna V. Palem, Georgia Institute of Technology Wayne Wolf, Princeton University General Co-Chairs: Shuvra S. Bhattacharyya, University of Maryland Trevor Mudge, University of Michigan Program Co-Chairs: Wayne Wolf, Princeton University Ahmed Jerraya, TIMA, Grenoble, France Coordination Vice-Chair: Bruce Jacob, University of Maryland Electronic Review Chair: Sungjoo Yoo, TIMA, Grenoble, France Tutorial Chairs: X. Sharon Hu, University of Notre Dame Joerg Henkel, NEC Publications Vice-Chair: Jack Davidson, University of Virginia Publicity Coordinator: Jalisa Norton, Georgia Institute of Technology Publicity Vice-Chair: Frank Mueller, North Carolina State University Representatives: Luciano Lavagno, University of Udine/Cadence, Italy (for Europe) Hiroto Yasuura, Kyushu University, Japan (for Asia) PROGRAM COMMITTEE Applications Subcommittee: Chair: Mani Srivastava Luca Benini, University of Bologna Sujit Dey, UCSD Marc Engels, IMEC Brian Evans, UT Austin Rajesh Gupta, UCI Paul Lettieri, Broadcom Viktor Prasanna, USC Asim Smailagic, CMU Gaurav Sukhatme, USC Ingrid Verbauwhede, UCLA Compilers and Operating Systems subcommittee: Chair: Jens Palsberg (palsberg@cs.purdue.edu) Rajeev Barua, University of Maryland Nikil Dutt, U.C. Irvine Rajiv Gupta, University Arizona Mahmut Kandemir, Pennsylvania State University Jens Palsberg, Purdue University Santosh Pande, Georgia Institute of Technology Eric Verhulst, Eonic Solutions, Germany Tools and Methodology subcommittee: Chair: Jan Madsen (jan@it.dtu.dk) Axel Jantsch, Royal Institute of Technology, Stockholm, Sweden Petru Eles, Linkoping University, Linkoping, Sweden Juergen Teich, Universitaet Paderborn, Paderborn, Germany Frank Vahid, University of California, Riverside Joerg Henkel, NEC Pai H. Chou, UC Irvine Wolfgang Rosenstiel, Eberhard-Karls-Universitat Tubingen, Germany Sri Parameswaran, The University of New South Wales, Australia Architecture subcommittee: Chair: Scott Mahlke (mahlke@eecs.umich.edu) Henk Corporaal, IMEC Carl Ebeling, Washington Paolo Faraboschi, HP Krisztian Flautner, Arm Mary Jane Irwin, Penn St. Bill Mangionne-Smith, UCLA Trevor Mudge, Michigan Herman Schmit, CMU Mukund Sivaraman, HP Labs SPONSORS Center for Research on Embedded Systems and Technology (CREST), Georgia Institute of Technology IBM